Design Engineer
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ACL Digital
Thane
JD 1: RTL Design Engineer – AI Experience: As per project need Location: Bangalore | Notice Period: 30 days Required Skills: - Strong RTL design using Verilog / SystemVerilog - Experience in AI/ML accelerator hardware - Design of MAC arrays, pipelines, datapath & control logic - Knowledge of systolic / vector / tensor architectures - Experience with AXI / AHB interfaces - Hands-on with RTL... |
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2 hours ago
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