Cyient jobs

DFT Technical Lead Job Description Experience: 10+ years - Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC...

Position: Sales Manager Cyient has established a strong presence in Design Led Electronics Manufacturing (DLM) Services across multiple industry segments. To sustain and deepen our presence in this services area, we are searching for a results-oriented sales leader who strives for excellence, is energized by new challenges, and is looking to expand key partnerships at a customer executive level....

Position: M&A Manager As part of the corporate development team, this role will focus on supporting and executing the organization’s M&A strategy, working closely with leadership to identify, evaluate, and integrate acquisition targets. The M&A Manager will prioritize developing a robust pipeline of acquisition targets, conducting financial valuations, and leading due diligence processes to...

Greetings from Cyient Ltd Cyient (formerly Infotech Enterprises Limited) is looking for DFT Engineers for an ODC based project Role: Senior/Staff Engineer- DFT Location: Bangalore/ Hyderabad Experience: 4-12 Years Job Description - Good knowledge of all the DFT concepts & ATPG Flows. - Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements. - Stuck-At, Transition...

We, Cyient is hiring for Engineer & Sr Engineer: IO Layout for End to End Offshore-Onshore Model based Global Product R&D Solution from scratch Experience Range: Engineer: 3-4 Yrs Sr Engineer: 5+ Yrs Base Location: Noida & Hyderabad Key Skills: Strong work experience in IO Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm. Hands on experience in any or...

Dear Candidate We, Cyient is hiring for one of the Senior position: Senior Staff Engineer: SOC Verification (Offshore-Onshore Model based Global Product Solution) Position. Base Location: Bangalore/ Hyderabad Experience Range: 5-12 Years Job Description: Looking for an experienced senior verification engineer with > 5 years of experience in ASIC/SOC/IP/block level functional verification...

We are looking to hire Strategy Director/Senior Director for Cyient, a leading Engineering Design and Technology Firm. The key responsibility of this role will be to identify, assess new business opportunities (new market, new sector, new industry etc.), recommend and incubate the business opportunity. The other roles and responsibilities may include driving special projects, developing strategy...

Dear Candidate We, Cyient is hiring for ASIC RTL Design Engineer (Offshore-Onshore Model based Global Product Solution) Position. Base Location: Bangalore Experience Range: 3-5 Years Job Description: - Good understanding of Verilog and design concepts - Hands on experience in RTL coding and verification - Good debugging skills - Scripting experience is a plus - Hands on experience in...

Dear Applicant, We, Cyient is hiring for Principal Engineer: SOC Verification for End to End Offshore-Onshore model based Global Product R&D Solution. Base Location: Bangalore/ Hyderabad Exp Range: 17-28 Yrs Budget: Open for Discussion Key Skills: 1. Candidate must have strong experience in SOC/ IP Verification Flow from scratch. 2. Candidate must have strong experience in UVM with TB...

Senior Engineer -- Analog Layout (8+ years of experience) Job Location: Hyderabad (ODC Project) Job Description - Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFet processes like 180nm to 3nm. - Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors,...

ASIC Engineer - DV Job Description - 8yrs of experience in Design verification - Developed verification methodology and testplan for new design - Good knowledge on the verification flows, SV and UVM - Perform RTL code coverage and functional coverage, formal analysis - Be responsible for defining the verification strategy and plan for the development - Develop coverage-driven verification test...

RTL Design / ASIC Design Lead / Architect Exp: 8 to 20 plus Responsibilities - 10+ years of experience in Semiconductor Industry. - Solid technical background with understanding and/or hands-on experience in Digital Design/ RTL Design - Participate in the architecture definition, implementation - Develop and implement RTL Integration, perform synthesis, implement on FPGAs and resolve timing...

Title: Engineer/ Lead - Physical Design location: Bangalore / Hyderabad Exp : 6 to 20 yrs. Job Description In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron...

Title: DFT Engineer / Sr.Engineer / Lead / Principal Engineer Exp 4 to 10 yrs. - Should have worked hands-on ASIC DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts...

Analog Mixed Signal Design-Staff Engineer Job Description - The candidate should have experience in Analog and Mixed Signal Design with focus on PMIC blocks such as DC-DC converter (BUCK,BOOST), LDOs and clocking circuits. Strong fundamentals of CMOS design, and active filter design. The various task involves, circuit design, validation, mixed signal validation, and reliability validation. -...

Dear Applicant We, Cyient is hiring for Sr Specialist/ Engineers: Analog Mixed Signal Circuit Design ( End to End Offshore-Onshore Model based Global Product R&D from Scratch). Experience Range: 3-5 Years Base Location: Hyderabad Budget: Open for Discussion, based on candidate expertise level. Pls note: We are looking for one of the finest Analog-Mixed Signal Circuit/ IC Design Specialist...

Dear Applicant,We, Cyient is hiring for Principal Engineer: SOC Verification for End to End Offshore-Onshore model based Global Product R&D Solution.Base Location: Bangalore/ HyderabadExp Range: 17-28 YrsBudget: Open for DiscussionKey Skills:1. Candidate must have strong experience in SOC/ IP Verification Flow from scratch.2. Candidate must have strong experience in UVM with TB Development from...

RTL Design / ASIC Design Lead / ArchitectExp: 8 to 20 plusResponsibilities10+ years of experience in Semiconductor Industry.Solid technical background with understanding and/or hands-on experience in Digital Design/ RTL DesignParticipate in the architecture definition, implementationDevelop and implement RTL Integration, perform synthesis, implement on FPGAs and resolve timing...

ASIC Engineer - DVJob Description8yrs of experience in Design verificationDeveloped verification methodology and testplan for new designGood knowledge on the verification flows, SV and UVMPerform RTL code coverage and functional coverage, formal analysisBe responsible for defining the verification strategy and plan for the developmentDevelop coverage-driven verification test plansKnowledge on...

DFT Technical Lead Job Description Experience: 10+ years - Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC...