Design Verification Engineer
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ACL Digital
Jamnagar
Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/System Verilog to create testbenches, write test cases, and debug failures. Coverage: Achieve functional and code coverage targets through constrained random and directed testing. Collaboration:... |
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4 hours ago
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