Mirafra Technologies jobs

Job Description- Position: Physical Design Engineer Preferred Experience : 5+ years Location: Noida NP: 0 to 30 days Roles& Responsibilities: PD activities involve Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , Scan chain hookup ,STA Constraints management , Floorplan, IR Drop, Placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS Tools : Design...

Mirafra Technologies Hiring Physical Design Engineers (Innovus) Engineers: Experience - 4 - 15 years Notice Period - 0 to 45 days Please find the Job Description Below: - Must hands on experience with a solid complex (SOC/sub-systems/SWRPs) implementation and strong understanding in PG/floorplan and physical design flows and methodologies, place and route using tools such as Innovus & FC, and...

Hiring STA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis. 🛠️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints, ECOs, low-power checks • Scripting:...

Position Title: Mixed-Signal Verification Engineer (AMS Verification) Location: Bengaluru Job Description Good fundamentals in analog and mixed signal circuit concepts and topologies. Experience working with mixed signal verification environment, simulation, and regression tools such as Cadence Virutuoso, Spectre, xCelium, Incisive, vManager, IMC Ability to read analog schematics and extract...

Position: DFT Director – Design for Testability (DFT) Location: Bangalore Experience Level- 12+ years in semiconductor design, with extensive expertise in DFT methodologies About the Role- We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT practice, ensuring we remain...

MIRAFRA TECHNOLOGIES HIRING PHYSICAL DESIGN LEAD Role: Physical Design Lead (RTL–GDSII) Experience: 10–12 years Location: Bengaluru, India (Hybrid / Onsite) Summary We are seeking an experienced Physical Design Lead to drive end-to-end RTL-to-GDSII execution for complex SoCs across advanced nodes, with strong ownership of PPA, timing closure, and team leadership. Key Responsibilities - Own...

🔹 Hiring: Analog Layout Engineer 🔹 Experience: 4+ Years Key Responsibilities: - Should have hands-on experience with TSMC 3nm and below nodes - Well-versed with Cadence's latest GXL and VSR router - Well-versed with Calibre PV on lower technologies - Excellent layout skills, such as device matching, routing matching - Ability to design hierarchical layouts Notice Period: 0 – 30 days...

Job-Linux Device Driver Engineer (LDD) Experience Required-4+ Location-Bangalore Joining Required-0-30 Days - Develop, enhance, and maintain Linux device drivers. - Work on Linux kernel internals to optimize and customize - Debug and troubleshoot system-level issues, ensuring prompt resolution of bugs. - Experienced with C++ and SOC

Mirafra is hiring for Emulation Engineers with 5+Yrs Emulation experience. KEY RESPONSIBILITIES: - BE/MTECH with 5+ years of experience in Emulation/FPGA - Create emulation models from RTL / Netlist. Develop hardware collateral to be integrated with the Palladium / FPGA emulation mode - Developing emulation testbenches to support necessary DV scenarios and firmware/software/hardware bringup. -...

Sr PD engineer Exp- 6 years+ - Full-Flow Implementation: Manage physical design from netlist to GDSII (Floorplanning, Placement, CTS, Routing). - Optimization: Improve timing closure, power (PDN, low-power design), area, and congestion. - Analysis & Verification: Perform STA, IR Drop, EM/IR, LEC, DRC/LVS checks. - Collaboration: Work with front-end (RTL) and validation teams. - Methodology:...

Mirafra Technologies Hiring DFT Practice Head Job Title: DFT Practice Head Location: Bangalore Job Overview: We are seeking an experienced and dynamic DFT (Design for Test) Practice Head to lead our DFT practice. The ideal candidate will possess deep technical expertise in DFT methodologies, along with proven leadership experience in building and managing a high-performing team. As the DFT...

We are seeking a highly skilled and motivated individual to join our team as a CPU Verification Engineer. In this role, you will play a critical part in ensuring the quality and functionality of our cutting-edge central processing units (CPUs) for a wide range of devices. Join us and be a part of shaping the future of computing. - Conduct thorough and rigorous testing of CPU designs to ensure...

SR DFT engineer/ Leads Exp- 4 years+ • DFT Tools flow: Mentor Tessent • Implementation: More RTL level implementation • LEC at RTL level (pre-DFT vs post-DFT) and gate level • SoC/Block : SoC as well as Subsystem/block/partition level • Good to have : SSN is must • Insertion: Scan, MBIST, occ, edt using ARM DFT flow • Patten generation, retargeting and simulation at block as well as...

Job description: Position: RTL Design Engineer Location: Bangalore Experience Level: 4+ years Notice Period - 0 to 90 days Roles& Responsibilities: - Should have experience with ASIC micro-architecture development - Expertise and hands on experience in Verilog/RTL design for IP/Sub-System or SoC. - Command and thorough knowledge on digital logic design concepts. - Should be good knowledge...

🔹 Hiring: Analog Circuit Design Engineer 🔹 We are looking for an experienced Analog Circuit Design Engineer Experience: 2-8 years Key Responsibilities: Proficient in designing high-speed SerDes Tx and Rx blocks, like: -Rx: CDR, CTLE, VGA, DFE, DeSerializer Notice Period: 0–90 days 📩 Interested candidates can reach out or share their profiles. Krithika M krithikamusale@mirafra.com

🔹 Hiring: SRAM Memory IP Layout Engineer 🔹 We are looking for an experienced SRAM Memory IP Layout Engineer who can independently handle memory layout development. Key Responsibilities: • SRAM Memory IP layout development • Calibre DRC/LVS verification • Leaf-cell development for SAM blocks Requirements: • 2–10 years of relevant experience • Strong hands-on experience with Calibre...

Job Description- Position: Physical Design Engineer Preferred Experience : 5+ years Location: Noida NP: 0 to 30 days Roles& Responsibilities: PD activities involve Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , Scan chain hookup ,STA Constraints management , Floorplan, IR Drop, Placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS Tools : Design...

Hiring STA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis. 🛠️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints, ECOs, low-power checks • Scripting:...

Mirafra is hiring for Emulation Engineers with 5+Yrs Emulation experience. KEY RESPONSIBILITIES: - BE/MTECH with 5+ years of experience in Emulation/FPGA - Create emulation models from RTL / Netlist. Develop hardware collateral to be integrated with the Palladium / FPGA emulation mode - Developing emulation testbenches to support necessary DV scenarios and firmware/software/hardware bringup. -...

Job Description- Position: Physical Design Engineer Preferred Experience : 5+ years Location: Noida NP: 0 to 30 days Roles& Responsibilities: PD activities involve Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , Scan chain hookup ,STA Constraints management , Floorplan, IR Drop, Placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS Tools : Design...